Plasma has long been employed for processing substrates (e.g., wafers, flat panel displays, liquid crystal displays, etc.) into electronic devices (e.g., integrated circuit dies) for incorporation into a variety of electronic products (e.g., smart phones, Computers, etc.).
In plasma processing, a plasma processing system having one or more plasma processing chambers may be employed to process one or more substrates. In each chamber, plasma generation may employ capacitively coupled plasma technology, inductively coupled plasma technology, electron-cyclotron technology, microwave technology, etc.
During the processing of a wafer, for example, reactant gas (which may employ one or multiple types of gases) is released into the plasma processing region and energized to form a plasma. For example, if the plasma is employed to etch the planar portion of the substrate (as opposed to the bevel portion), the plasma is confined to the plasma processing region that is centered above the substrate and is generally bounded by the substrate, the upper electrode or upper chamber wall/component and/or the confinement ring set. The plasma is then employed to etch, deposit, or otherwise process exposed areas of the wafer surface
During processing, the plasma interacts with exposed areas on the substrate, which interaction both processes the exposed areas and generates by-products. The by-product gas is then pumped away as plasma continues to be generated from the supplied reactant gas. Other components in the plasma (either ions or radicals) may form certain pre-cursors that are critical for the side wall protection of etched structures to assure an anisotropic etch. By way of example, such pre-cursors may result in polymer deposition on feature sidewalls to improve etch directionality. Other pre-cursors may advantageously result in certain etch selectivities between films of different material which would be hard to accomplish otherwise.
FIG. 1 shows a conventional plasma processing chamber 102 in a plasma processing system (which may have one or multiple chambers). In FIG. 1, substrate 104 is shown disposed on an electrostatic chuck (ESC) 106 forming a lower electrode. Insulator ring 108 and ground ring 110 are shown surrounding ESC 106. Plasma processing region 120 is shown bounded by a chamber ceiling 122, lower electrode/ESC 106, and a set of confinement rings 124. In the case of a capacitively coupled plasma processing system, chamber ceiling 122 may represent the upper electrode, for example. In other systems, the chamber ceiling may simply represent a chamber structure for confining the plasma.
Reactant gases are supplied from external gas supplies (conventional and not shown) via gas plenum 130, which may also include heating apparatus to control the temperature of upper electrode 122. In the example of FIG. 1, plasma processing chamber 102 is a capacitively coupled plasma chamber and thus chamber ceiling 122 may represent an upper electrode, which may be grounded or may be provided with RF energy for example.
A plasma generation power source 170, in the form of an RF power supply in the example of FIG. 1, supplies RF energy to lower electrode/ESC 106 to ignite a plasma in plasma processing region 120. In other chamber designs or in chambers using different plasma generation technology, the plasma generation power source 170 may include multiple power sources to provide RF energy to different components of the chamber or may be another type of plasma generation technology other than RF (such as microwave, for example).
By-product gas may be exhausted either through chamber side or chamber bottom or both. The components of plasma processing chamber 102 as well as other existing plasma generation chambers using capacitively coupled plasma or other plasmas generated using different plasma generation technologies are conventional and well known to those skilled in the art and will not be elaborated here.
It has been observed that in some plasma processing chambers, a certain degree of process non-uniformity (in terms of processing rate or processing result) exists from the center region 150 of substrate 104 to edge region 152 of substrate 104. When etching in narrow-gap chambers (narrow gap chambers represent chambers wherein the gap between the substrate upper surface and the lower surface of the upper electrode may be less than 10% of the substrate diameter) and/or processing larger substrates (such as 450 mm wafers or larger), non-uniformity issues tend to exacerbate.
In some cases, etching of high aspect ratio features tends to suffer from a phenomenon known as ARDE (Aspect Ratio Dependent Etching). Some evidence suggests that one mechanism responsible for ARDE is the relatively long time it takes for reaction by-products from the lower parts of deep structures such as high aspect-ratio holes (or trenches) to diffuse out to the surface of the wafer from where they can be pumped away. The increased abundance of etch by-products at the bottom of deep features slows down the re-supply of new etchants thereby reducing their concentration. This leads to a slowing of the etch front compared to the rate just beneath the mask as the front advances deeper into the feature
In view of the foregoing, improved etching techniques and apparatuses are desired.